资源列表
complex-mul
- complex multiplier in verilog code is uploaded
verilocode1
- verilog code1 of 32bit divider is uploaded
Mini-project-code1
- 4 bit booth multiplier is uploade
verilog-code5
- 16*8 sram is uploaded
Layman-Fun-PFPGA
- 玩转FPGA是一个适合初学者的FPGA的优秀指导资料，详细的例程，详尽的解释，有助于初学者快进入状态-Excellent guidance information, Fun FPGA is suitable for beginners FPGA detailed routines, detailed explanations, help beginners fast into the state ...
j_k
- jk counter using verilog
three2eight
- 用vrilog语言写的一个三八译码器，当一个选通端（G1）为高电平，另两个选通端（/(G2A)和/(G2B)）为低电平时，可将地址端（A、B、C）的二进制编码在一个对应的输出端以低电平译出。-Write the language VRILOG a thirty-eight of the decoder, when a strobe terminal (G1) is high, another two strobe terminal (/ (G2A)/(G2B)) is low, the addr
Basic_Blocks_VHDL_Code
- it is some codes in vhdl
NIOS
- nios那些事儿源码合集，一些常用的nios源码，建议新手，值得看信下-nios thing source collection, used nios source, it is recommended that novice, is worth the read the letter
vhdl
- 新手学习vhdl语言在quartus上编写的12个程序，能完成与非门等简单功能的小程序-Novice learning vhdl language written in quartus 12 program, to complete a small program with simple functions such as NAND gate
clock
- FPGA时钟，vhdl，带设置时间，暂停，开始-FPGA clock
8b10b_encdec_latest.tar
- 8b10b编码的FPGA ipcore, 8b10b编码的FPGA ipcore-The 8b10b encoding of FPGA ipcore of 8b10b coding-FPGA ipcore, 8b10b coding the FPGA ipcore of