资源列表
CICzhengli
- 整合本站所有CIC滤波器能用的下载，并给出最好的选择，节省您的时间，花一次费用享受多次代码下载-Integration site CIC filter can download and gives the best choice, saving you the time to spend a one-time cost to enjoy several Codes
fpgaUPDW
- fpga上下变频混频实现，其中CIC采用多种方法设计，自己花两个星期编写，中文注释，浅显易懂-fpga up and down conversion mixer implemented which CIC using a variety of methods designed, he spent two weeks writing notes in Chinese, easy to understand
MS-final-project
- DLX 5级流水 实现所有功能 包括跳转指令-DLX 5 stage pipeline to achieve all functions including jump instruction
div
- 两个3位二进制数的除法，结果（整数商）输出到数码管显示-verilog multply
FPGA_CPLD-SHC
- FPGA_CPLD-SHC多款FPGA CPLD开发板的原理图，很好的线路设计参考-FPGA_CPLD-SHC Variety of FPGA CPLD development board schematics, a good reference circuit design
lcd3
- FPGA驱动lcd1602代码，使用标准三段式状态机编写-FPGA LCD code
DAbx
- 基于FPGA的并行FIR数字滤波器的实现-FPGA-based parallel FIR digital filter implementation
VGA_ROM
- FPGA驱动VGA 显示图片的完整代码，经测试可用，ROM中已经保存有一个图片的rgb信息，大家也可以更改图片，去网上下载一个RGB提取的程序就可以了，把图片rgb信息保存在ROM里-FPGA VGA CODE
verilog_Manchester
- verilog—Manchester 极为简单的曼彻斯特编解码 verilog实现 分为编码和解码两个部分 通过自己测试 同步异步均正常收发-extremely simple verilog-Manchester Manchester codec verilog achieve synchronization through their own test is divided into two parts of the encoding and decoding Asynchronous w
lcd_flash
- \LCD_FLASH 一个用 NIOS写的完整的LCD演示程序.并且程序可以下载到FLASH 内运行. -LCD IN NIOS FOR NIOS VER4.0 for EP1C12
lcd_init
- 用Verilog HDL编写的LCD显示屏刷屏程序-LCD display refresh program written using Verilog HDL
SD_Card_test
- SD卡读写程序,SPI接口实现，采用verilog hdl实现- SD read and write test