资源列表
偶数分频器源代码（可移植）
- FPGA奇偶分频器 可移植 原工程文件 试验没有问题-The FPGA parity divider, portable the original project file
gk
- a verilog code of 3 input and gate.
MP3
- MP3 decoder. dkfjgldfmgmxc,.vx fhf hbfgbmlvmcb fghl;fb;c hgfgnlg
Electronic design
- Is a code that detects peaks on a signal.
design
- This is information about design
iic总线源代码
- 此文件是iic总线驱动的源代码文件，iic.c 可以读写控制多个挂在总线上的器件。
sobel2
- 新的sobel算子的FPGA实现。使用verilog语言，并调试通过~-The sobel operator new FPGA implementation. Verilog language, and debugging through to
median_filter
- 中值滤波的verilog实现，完整工程，调试通过-Median filter verilog achieve complete engineering, debugging through
uart
- UART 串口收发程序 VHDL UART 串口收发程序 VHDL-UART serial port transceiver procedures VHDL
S1_38yima
- EP1C6，38译码器的简单代码，已编译通过-EP1C6 38 decoder simple code, compiled by
S6_VGA
- EP1C6实现VGA显示，已经通过编译，请使用-The EP1C6 achieve VGA display, has been compiled, please use
DMA_TOP
- vhdl code of dma module