资源列表
Verilog
- Verilog语言练习与讲解中文版.pdf-Verilog language exercises and explain the Chinese version. Pdf
DDS_100325(13)_success
- QUARTUS II环境下VHDL语言编写DDS程序，双数字信号输出，一为正弦波幅值输出，一正弦波差值信号。时钟2^21HZ，带24bits频率控制字。-QUARTUS II environment, VHDL language DDS program, two digital signal output, an amplitude for the sine wave output, a sine wave difference signal. Clock 2 ^ 21HZ, with 24bi
190.7_Freq_divider
- QUARTUS II环境下VHDL编写的小数点分频器程序，实现190.7分频，可以将50MHz时钟频率分频成约等于2^21Hz频率，方便特殊情况下的运算-QUARTUS II, prepared under the decimal divider VHDL program to achieve 190.7 frequency, you can divide into a 50MHz clock frequency is about equal to 2 ^ 21Hz frequency, eas
deng
- 彩灯电路，Quartus7.2，幕布式，移动式-deng Colourful light electric circuit, Quartus7.2, act cloth type, ambulation type
SOPC
- 能显示时、分、秒，24小时制；可设定夜间某个时段不报时；-Can display hours, minutes, seconds, 24-hour system can set a time at night is not the newspaper
I2C-BusDesign
- 本程序给出了完整的I2C设计工程文件及VHDL源代码-This procedure gives the complete design of the project file and I2C VHDL source code
serial-VHDL-Deign
- 本程序模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。-This procedure is to verify the function module and the PC machine to achieve a basic serial communication functions. Need to install a serial PC, debugging tools to verify functionality of the
LCD-VHDL-Design
- 本程序模块的功能是验证实现LCD液晶显示。-This procedure is to verify the function module to achieve LCD liquid crystal display.
AD_TLC549_TEST
- 本程序模块实现在FPGA内部的AD转换模块。模拟AD_TLC549转换器。-The program module within the AD converter in the FPGA module. Analog AD_TLC549 converter.
multiply
- 简单的乘法器，用Verilog实现 multiply-multiply
add
- 加法器，用硬件汇编语言实现 A-Adder in hardware assembly language