资源列表
2008081014094045
- 步进电机细分ip核，闭环回路反馈，详见注释-Ip Subdivision stepper motor nucleus, closed loop feedback, see note
apb_spi
- Simple SPI interface realization on Verilog HDL with parameterized FIFO and APB interface
v7
- Here is a Fifo impementation in vhdl with a 8 bit input and 8 bit output, reset and a synchronisation for reading and writing with different clocks
VHDL-common-errors
- 本文给出了vhdl仿真的常见错误及其有交效的改正措施-VHDL common errors
Converte_integer_to_bcd
- VHDL code for INTEGER conversion (0-255) to BCD code for display
Counter_Design_Block
- Here is a code for a simple counter based on verilog
lab6
- this verilog file gives the user an ability to program the switches on an altera board
VHDL-7
- VHDL useful website links-VHDL useful website links
xapp345_verilog
- Synthesizable Verilog UART source code.
CRC.C
- 下面以最常用的CRC-16为例来说明其生成过程。 CRC-16码由两个字节构成，在开始时CRC寄存器的每一位都预置为1，然后把CRC寄存器与8-bit的数据进行异或(异或：二进制运算 相同为0，不同为1；0^0=0 0^1=1 1^0=1 1^1=0)， 之后对CRC寄存器从高到低进行移位，在最高位（MSB）的位置补零，而最低位（LSB，移位后已经被移出CRC寄存器）如果为1，则把寄存器与预定义的多项式码进行异或，否则如果LSB为零，则无需进行异或。重复上述的由高至低的移位8
id
- 用vhdl写的流水线译码阶段，绝对好用-Written in line with the vhdl decoding stage, absolutely easy to use
FFT_090808
- FFT变换的FPGA实现程序，对于信号处理非常有用。-FPGA implementation of FFT transform, is very useful for signal processing.