- C#
- PLL Programs for the book of Phase Locked Loop :design simulation and applications
- MD2Loader_OGL 大名鼎鼎的MD2模型的导入示例程序
- Introduction_to_Classical_Chinese_version_of_JSF_i JSF入门经典资料中文版Introduction to Classical Chinese version of JSF information
- SPI_LoopBack_Interrupt A SPI
- deletfile Application for douplicated files
资源列表
zhuangtaiji
- 用状态机实现序列检测器的设计，并对其进行仿真和硬件测试。-With the sequence detector state machine design, and its simulation and hardware testing.
jibengongtestbench
- testbench的基本写法，双口ram,双端口的编写 -The basic writing testbench, dual-port ram, dual-port the preparation of
FIFOverilog
- 在FPGA进行数据的缓存，在跨时钟域应用较为广泛-Data cache, in the widely used cross-clock domain
fpga_fmsc
- 本代码在FPGA上实现了与STM32单片机的FSMC总线通信的时序代码，在ALTERA FPGA上得到验证。-The code on the FPGA to achieve with the STM32 microcontroller timing code FSMC bus communication is verified on ALTERA FPGA.
mimasuo
- 4weimimasuo 可运行 可仿真 -aetgdffh tghj tjfgj fdg vbn t
vhdl-examples
- 这是eda初学者可以借鉴的两个关于电子频率计的VHDL设计实例
frame_syn
- 通信系统中数据的传输以帧为单位，在FPGA中帧头检测是通信系统中的一部分，该程序实现了FPGA中帧头的检测。-Transmission of data in a communication system in units of frames, the frame header is detected in the FPGA part of the communication system, the realization of the frame header is detected in th
FIFOverilog
- 异步FIFO实现数据先入先出的存储方式基于verilog HDL语言-Asynchronous FIFO first-in, first-out data storage based on Verilog HDL language
amba_sim_code
- AMBA Protocol implementation using VHDL
B325_Assignment
- Assignment for a project
AHB_APB_leon_SYNvhdl.tar
- code regarding the ahb
32-crc32
- 32位数据输入并行算法Verilog HDL代码。-32 bits of data input and parallel algorithm Verilog HDL code