资源列表
cpu_lynn
- Verilog 实现的 简单 单线程 CPU， 基于计算机组成书目， 思路清晰， 有测试平台。-Verilog realization of a simple single-threaded CPU, the composition of computer-based bibliography, clear lines of thought, a test platform.
s
- 时序程序-Timing procedure
vhdl--example
- hello iam a coding word for you to doing vhdl h-hello iam a coding word for you to doing vhdl hoo
MX29LV320D
- 32M-BIT CMOS Voltage 3V Flash Memory
QuartusII-about-warning
- 主要是介绍quartus编译过程中出现的问题和解决方法，希望对大家有帮助-Introduce the quartus compile process problems and solutions, I hope to you
RSdecoder
- 自己写的基于verilog的RS译码器，能够实现RS(240，224)码译码，一级流水设计，可连续译码也可非连续译码。-RSdecoder for RS(240,224).
request_arbiter
- // Inputs --- // DMACSREQ_i -- The 16-bit signal which stores the single request of all the 16 devices // DMACBREQ_i -- The 16-bit signal which stores the burst request of all the 16 devices // hclk_i -- Clock signal // hresetn_i -- Active l
mulfp
- Mulfp for vhdl coddin-Mulfp for vhdl coddingg
vhdl-code-for-jk-flip-flop
- vhdl program of jk flip flop. positive edge triggerd. the test bench is also available with the code. a simple program to start with vhdl
111
- 51单片机设计的电子密码锁 -51 Single-chip design of the electronic code lock
verilog
- basic verilog codings in fpga
DE2_NIOS_HOST_MOUSE_VGA
- Verilog代码，适合于初学者进行学习，是基于DE2平台的代码。