资源列表
fir_lms
- 基于FPGA的自适应滤波器的实现。采用Verilog编程，2阶滤波器。-FPGA-based realization of the adaptive filter. Using Verilog programming, 2-order filter.
source_verilog
- 基本VERILOG模块，有相当多的功能，慢慢欣赏吧
UDP_receiver
- this is udp receiver application for sending packets through the ethernet
vhdl2
- some vhdl sourcecode for freshmen
digital_watch
- Verilog code of digital watch
decryption
- AES decryption in VHDL!! Wit LCD controls
FPGA_BUS
- 采用ACTEL的FPGA实现外部并行总线与MCU进行通信，完成I/O扩展与串口扩展功能。-ACTEL FPGA implementation using the external parallel bus to communicate with the MCU to complete the I/O expansion and serial port expansion.
VHDL_examples
- contain simple examples in VHDL languge
DDS4.mdl
- DDS(快速正交调制）生成正弦波形，利用相位累加字进行累加，查找查找表内容输出正弦数据，在通信领域应用很多，我采用的是matlab的simulink进行前期仿真-DDS (fast quadrature modulation) to generate sine wave, the use of the word to accumulate phase accumulation, content output sine lookup table lookup data in many applic
englishword
- 这是电子通信行业fpga应用英文缩略语表，对工程技术人员有很高的参考价值-english words
C8051F340
- 基于led,lcd，显示的程序课题设计练习-led,lcd 显示的程序课题设计练习
fenpin
- 这个一个多次对时间进行分频的程序，这种方式可以避免同步跳转带来的干扰-A multiple time divided by the program, in this way to avoid synchronized jump to the interference caused by