资源列表
zdsylj
- 自动售饮料机，在quartusII平台上实现verilog源代码。很好用。-Beverage vending machine, quartusII platform to achieve verilog source code. Good use.
fpga-iic
- 基于FPGA的模拟IIC接口设计与实现，FPGA及片上系统SOPC应用 。-FPGA-based simulation IIC interface design and implementation, FPGA and SOPC System on Chip Applications
vga
- vga，视频显示源代码，很好用，自己在板子上看看，我用了成功了。-vga, video display source code, very good, and their look on the board, I used a success.
sdram
- sdram的quartusii实验源代码，和大家分享。很好用，我在自己的开发板上实现了他的功能，大家试一下。-sdram of quartusii experiment source code, and share. Very good, in my own development board realize his function, we try.
rs232
- rs232串口通信实验4位的串口，verilog源代码。-rs232 serial communication experiment 4 serial, verilog source code
dgnszsz
- 多功能数字钟，在quartusII软件平台上实现的verilog源代码。大家试试看。-Multifunctional digital clock in quartusII software platform to achieve the verilog source code. We try.
hlh
- 绿灯、黄灯和红灯，交通灯实验veril源代码，与大家分享，在quartusII平台上实现。-Green, yellow and red lights, traffic lights experiment veril source code, to share with you, in quartusII platform.
zwcfq
- 带置位和复位端的1 位数据锁存器，源代码verilo实现，在quartusII平台上，大家试试看。-With set and reset terminal a data latch, the source code verilo achieve, in the quartusII platform, we try.
HY57V64_control
- 本代码用verilog而不是直接在nios中用ip核来实现HY57V641620FTP-6的读写，时序完全正确，从串口输出来验证的数据完全正确。附带说明和参考资料。希望对您有帮助。-This code is used instead of directly in verilog ip core nios used to achieve HY57V641620FTP-6 reading and writing, the timing exactly right, from the serial d
fft_prj_final
- 基于FPGA的利用傅里叶变换将音频信号转化为图形通过VGA接口输出到显示器上。-FPGA-based Fourier transform of the audio signal into a graphical output via VGA connector to the monitor.
15-vlsi
- Asynchronous fine grain power gated logic paper get code and logic static used
modelsimPdebussy-batch-processing
- 内容包括采用Windows批处理方式高效执行Verilog仿真验证的方法，采用Modelsim+debussy联合仿真，里面包含一个加法器实例，批处理文件，仿真指令等。-Included with Windows batch efficient implementation of Verilog simulation method, using Modelsim+debussy co-simulation, which contains an example of an adder, batch