资源列表
decode
- 使用FSM控制，完成32位数据的decode，对DATA_PATH进行监测，Load Return addr from Stack into PC-Using FSM control, complete 32-bit data decode, for DATA_PATH monitoring, Load Return addr from Stack into PC
stoto
- 通过选通可以分别实现四个5位数据的简单逻辑运算和数学运算-Gating can be achieved through four five data were simple logic operations and math
bhsvhdl
- I uploaded vhdl progrgrams on AND gate, JK flip flop,OR gate, Xor gate
LED_Test
- 利用VerilogHDL在quartus ii下编写的简易流水灯实验，采用的是顺序执行的方式！-Use in quartus ii VerilogHDL summary prepared under light water experiment, using sequential way!
DDR3-SDRAM-Controller
- DDR3的控制器（并带有Testbench），可烧录到FPGA中对内存进行读写，相关技术人员可在该代码上修改用于其他场合-DDR3 controller (with an Testbench), the FPGA can be burned to the memory read and write, the relevant technical staff can modify the code to be used on other occasions
mini_aes_latest.tar
- It is minimal version of AES verilog implementation. It is really simple and easy to understaning.. works well manual included. Enjoy!
v6Integrated-Block-for-PCIE-UG
- 赛灵思官方公布的PCIE集成端点核设计用户指导，是FPGA从业者的好帮手-Xilinx Integrated Endpoint official PCIE core design user guide, is a good helper for FPGA practitioners
EDK-preliminary-guidelines-for-use
- EDK初步开发使用指南，对于初学者是很好的学习资料-Initial development EDK user guide, for beginners is a good learning materials
ISE-and-Modelsim-simulation
- ISE和Modelsim联合仿真指导材料，适合初学者看-ISE and Modelsim co-simulation guidance material, suitable for beginners
verilogiic1121
- 一个基于verilog的iic协议的控制器，用状态机结构编写，可以将数据写入eeprom中，再读出来。-A protocol based on verilog for iic controller state machine structure with writing, data can be written to the eeprom, reading them out.
uartfifo
- 一个基于verilog的fifo的例子，由数据产生模块产生数据传到fifo中，然后同过发送模块将数据发到上位机上。-One based on the fifo verilog example, by the data generation module generates data to the fifo, and then sent over the same module sends data to the host computer.
EX7
- 一个基于verilog的串口接收发送模块，可与上位机通信。-One based on the serial receiver sends verilog module can communicate with the host computer.