资源列表
RS232_R_T
- 基于FPGA的verilog语言的串口通讯的数据接收和发送模块的程序-The data receiving and sending module of FPGA serial communication program based on Verilog language.
fpga-spi-to-uart
- FPGA的SPI转多路UART / 485-spi to uart or 485
FIFO
- 基于FPGA的8位fifo 1s发送10个8位数据，采用的是verilog 编程语言，入门，方便各位学习-Eight fifo based on FPGA 1 s sent 10 8 bits of data, USES is verilog programming language, introduction, convenient for you to learn
verilog_HDL-basic-course
- verilog的精简教程，很容易看懂，包括了verilog的基本语法和一些基础例子-streamlining verilog tutorial, very easy to understand, including the basic verilog syntax and some basic examples
SPItoIICcodeForAlteraCPLD
- Altera 官方关于SPI和I2C应用的CPLD实现的例子-About SPI and I2C official Altera s CPLD implementation examples of applications
Xilinx_xapp341_uart_verilog
- Xilinx应用笔记关于UART的verilog实现方法和例子说明-Xilinx application note on the UART verilog implementation methods and examples
xapp341_verilog
- Xlink应用例子关于UART的Verilog实现的源代码-Xlink application examples about UART Verilog realization of the source code
verilog_uart_valid
- 用verilog语言写uart通讯的原理以及经过验证的源码-Uart verilog language written with the principle of communication and a proven source
modelsim-se-10.1a-crack
- modelsim10.1a的破解文件，已测好用，破解简单-modelsim10.1a crack file, have been measured easy to use, simple crack
pwm_simple
- 一个非常容量理解的PWM模块，采用了计数器的原理设计，可以用来扩展-A great capacity to understand the PWM module, using a counter design principle, can be used to extend
mul24_out48
- 24位数据和24数据相乘得到28位结果。注重面积的优化，采用时钟循环加减的做法。-24-bit data and 24 data obtained by multiplying 28 results. Focus on the area of optimization, the use of the clock cycle subtraction approach.
infrared_carrier
- 红外载波的发送模块，可以用于载波产生，设计很简单，容易看懂。-IR carrier transmission module can be used for carrier generation, the design is very simple, easy to understand.