资源列表
ZRtech-CORE
- 淘宝卖家ZRTECH核心板的程序与PDF说明-ZRTECH core board procedures and instructions PDF
1602test
- Verilog AD转换1602显示，用QuartusII编写的。完整的工程，好使！-Verilog AD converter 1602, with QuartusII prepared. Complete works, so that!
shift_register8
- XilinxFPGA Verilog 8位的移位寄存器-XilinxFPGA Verilog 8-bit shift register
flipflop_d
- Xilinx Verilog D触发器 绝对好用-Xilinx Verilog D flip-flop is absolutely easy
8-way-Responder
- 8路抢答proteus 说明：1，该抢答器，复位时刻，显示计时位0秒. 2，待主持人宣布完问题后，按下开始计时按钮，则等待8位选手抢答： 若有人抢答，则在显示屏上显示出选手编号，让其回答问题，并倒计时20S，限制20S的作答时间；若无人抢答，则重新开始计时，这时需要主持人再次按下开始按钮； 3，在这之前，若主持人还未宣布开始，若有人抢答，则宣布犯规，并且显示出相应的选手号码，给出相应的惩罚；-8-way Responder proteus Descr ipti
N-bits-by-M-bits
- 这是一个verilog代码实现的常用乘法器。设计的是通用N比特乘M比特的二进制乘法器-This is a common multiplier verilog code. Design of a generic N bits by M bits of the binary multiplier
randomization
- 伪随机序列应用设计:利用verilog代码实现伪随机信号的产生-Pseudo-random sequence application design: the use of pseudo-random signals verilog code generation
CRC_Tst
- 关于CRC的发射，以及接受的验证，用Verilog实现，包含testbench验证-About CRC launch, as well as acceptable verification, using Verilog implementation, including verification testbench
pingpongf16
- 使用quartusii软件,用verilog语言编写，通过DE2-70板在屏幕上实现乒乓球动态效果。-Use quartusii software, using verilog language, through the DE2-70 board on the screen to achieve tennis dynamic effects.
tequan
- 特权同学 深入浅出玩转FPGA视频教程里面的verilog代码-Fun privileged classmates easy video tutorials inside FPGA verilog code
lab-1
- Lab1 from altera this is basic is getting to you
lab-1.2
- this is lab2 from altera