资源列表
lab-1.3
- thisi s lab3 from altera
cpu_store
- VHDL语言制作CPU，8位，16条指令，能够完成多种操作. -VHDL language production CPU, 8-bit, 16 instruction, to complete a variety of operations. VHDL language with CPU, 8-bit, 16 instruction, to complete a variety of operations.
CPU_z
- 上计算机组成原理课时，老师提供给我们的简单8位CPU。-On computer organization class, the teacher give us a simple 8 CPU.
Verilog_COMPLEXCLOCK-v2013.10.07
- 电子钟，闹钟，秒表，可调时间，采用6位数码管显示-Electronic clock, alarm clock, stopwatch, adjustable time, the use of six digital tube display
Verilog_CLOCK-v2013.10.07
- 六位数码管显示的电子钟，可以调整时间，通过验证-Six digital display electronic clock, you can adjust the time by verifying
CPLD_LCD
- 用verilog编写的1602显示屏的程序，通用性较强，测试平台是DE0-Written in verilog 1602 Display of the program, versatility is strong, the test platform is DE0
ads805
- 电设用到！用verilog编写的TI的ADS805的调试程序。测试平台是DE0 。-Electric facilities used! TI' s written in verilog ADS805 debugger. Test platform is DE0.
vga_cd
- 用verilog编写计数程序，在VGA上显示的，适合VGA的初学者。测试平台DE0 。-Counting program written in verilog, displayed on the VGA, VGA suitable for beginners. Test platform DE0.
dianzhen_game
- 用verilog编写的点阵游戏，具有蜂鸣器音效，涉及并转串芯片74HC595，1602显示等。-Written in verilog Dot Game, with a buzzer sound, involving parallel and serial chip 74HC595, 1602 display.
pingp16
- 改进后的pingpong实例，增加球数至16个，用于检测vga输出,并由相应ucf文件-Improved pingpong example, to increase the number of balls 16, for detecting vga output
traditional_fft
- 2048点fft的VHDL实现 可综合-2048 FFT implementation synthesis
QII_Intro_CN
- FPGA的入门教程，每一个都有说明，按照说明仔细的练习可以很快掌握FPGA-FPGA introductory tutorial, each with a descr iption, follow the instructions carefully exercises can quickly grasp the FPGA