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资源列表
dpll2
- 数字锁相环的vdhl实现，鉴相器，计数器，压控振荡器，和分频器-Vdhl DPLL implementation, the phase detector, a counter, a voltage controlled oscillator, and a frequency divider
Altera_FPGA_CPLD
- Altera_FPGA_CPLD学习笔记 特权整理完善-Altera_FPGA_CPLD study notes privilege perfect finishing
Verilog-Template
- verilog 常用功能模块的实例，代码可以直接复制使用-verilog examples of commonly used function modules, the code can be directly copied using
ethernet.tar
- verilog写的以太网硬件模型，使用xilinx FPGA，ieee802.3ae-an ethernet model in Verilog，using a Xilinx FPGA，and the function：IEEE 802.3ae Media Access Control (MAC) Parameters, Physical Layers, and Management Parameters for 10 Gb/s Operation
ADDER16B
- 16位加法器,用于计算比较大的数据，希望对大家有帮助，多点下载，非常感-sixty bit adder
ARITHMETIC
- 算术乘法器，这是我自己设计的算术乘法器，是用VHDL语言设计的，希望对大家有帮助-Arithmetic multiplier, this is my own design arithmetic multiplier, is designed with VHDL language, and they hope to help everyone
EX16
- verilog 一个小程序 关于DS18B20 的驱动程序-verilog a small program on DS18B20 driver
police_siren
- 警察车的声音，利用verilog编写，可以下载到PFGA，已经在altera cycloneIII芯片上验证成功-The sound of the police car, use verilog to write, can be downloaded to PFGA, has proved to be successful on the chip altera cycloneIII
freq_viewer
- quartusii下基于原理图方式构建的频率计，在altera cyloneIII 芯片上已经验证成功，精度为1Hz-quartusii under way to build a schematic-based frequency meter, in altera cyloneIII chip has proved to be successful, the accuracy of 1Hz
vhdl-programs
- vhdl source codes for various digital systems
IIC_EEPROM
- IIC_EEPROM是通过IIC传输方式与EEPROM金星数据传输的Verilog工程原文件。-IIC_EEPROM by IIC transmission of data transfer with EEPROM Venus Verilog project the original file.
multiplier
- 乘法器的verilog工程文件，可以进行仿真实验，有详细解释，适合初学者学习参考。-Multiplier verilog project file, can be simulated, with detailed explanations, suitable for beginners to learn.