资源列表
PLD_tips
- PLD设计技巧——消除组合逻辑产生的毛刺 PLD设计技巧——采用同步电路设计 PLD设计技巧——提高FLEX器件的系统速度 PLD设计技巧——如何处理内部三态电路 257K PLD设计技巧——多时钟系统设计 314K PLD设计技巧——用单片机配置FPGA PLD设计技巧——如何处理建立/保持(Setup/hold)时间 -PLD design skills- to eliminate glitches generated by PLD combinati
Vhdl_Guide
- VHDL黄金参考手册，包括VHDL语言的语法特点，综合以及常用硬件设计实例。-VHDL golden reference guide The VHDL Golden Reference Guide is a compact quick reference guide to the VHDL language, its syntax, semantics, synthesis and application to hardware design.
FPGA_Design_tip
- FPGA设计技巧，锁存器与寄存器区别，状态机设计，门控时钟等-Improving Performance in Complex Programmable Logic Devices (CPLDs) with the FPGA Express Software
FPGA_design_process
- FPGA 设计全流程：Modelsim>>Synplify.Pro>>ISE-FPGA design of the whole process: Modelsim>>Synplify.Pro>>ISE
digal-clock-VHDL
- 一个数字电子钟的设计，有VHDL并含电路图-A digital electronic clock design of the VHDL and the circuit containing
asi_framesync
- 从串行TS流中找到同步头,生成标准并行TS流的方法!-Be found in TS stream from the serial sync header to generate the standard method of parallel TS stream!
CONVOLUTIONAL_INTERLEAVER
- DVB数据交织,交织深度I=12,已得到应用!-DVB data interleaving, interleaving depth I = 12, has been applied!
RS_ENCODER
- DVBC RS编码,标准TS流输入输出接口!-DVBC RS encoder
lowpassfir
- Low pass fir filter for ecg signal in VHDL
SLAVE_FIFO_16BITS
- 68013和FPGA通信 含有68013 slave firmware 含有FPGA VHDL程序-communication between 68013 and FPGA including 68013 slave firmware including FPGA VHDL code
ddr2_controller
- DDR2控制器设计原码,可以在FPGA上测试通过,并对外部的ddr memory进行读写访问.-DDR2 controller design of the original code, can be tested through the FPGA, and external ddr memory read and write access.