资源列表
Verilog_uart
- UART communication code
DSPHBControl
- DSP Example Code for programming an Hybrid AC/DC converter-DSP Example Code for programming an Hybrid AC/DC converter
thesis_all
- VHDl code for USB microcontrolel
2.CLK1HZ
- make 1hz clk, using xc95144 CLPD
fir_1
- 这个FIR滤波器是基于ALU框架编写的，仅供参考使用-The FIR filter is based on the framework of the preparation of ALU, the only reference to the use of
Stopwatch
- 这个设计是电子科技大学集成电路综合课程实验的项目，主要内容是跑表-This design is the University of Electronic Science and Technology Experiment IC integrated curriculum project, the main contents of stopwatch
4_bit_counter
- 4 bit counter with vhdl code
Clock_Full
- clock program on altera de2-70 board
project_Giovanni_DAliesio
- code for accumulator multiplier
vhdl2
- vhdl book to design
vhdl1
- about architecture of entity about vhdl design
vhdl
- vhdl book for design