资源列表
registers
- in this coding are used to realize the synties and beherival modeling in vhdl
memory
- the memory program are used to design the fpga application for in very log module
FIR
- The first three examples illustrate the difference between RTL FSMD model (Finite State Machine with Datapath buildin) and RTL FSM + DataPath model. From view of RT level design, each digital design consists of a Control Unit (FSM) and a Datapath. Th
pgm
- uart vhdl code contains all the neceesary things for a uart of speed 2 mbps and has a fifo of 64 KB
flowvhdl
- 16 bit adder source code.
DP_RAM.v
- tis about dpram... if u have any quries fell free to ask -tis is about dpram... if u have any quries fell free to ask
fifobaseddprammemory
- This file if about DPram based fifo storage... wirte and read in both ports
sqrt_LUT8
- Square root calculation: S=N^2+d using LUT-Square root calculation: S=N^2+d using LUT
fifoed_avalon_uart9.1_applicaton
- 用于Altera Avalon总线的、具有FIFO缓冲的Uart数据串口IP核以及应用于Nios2的、真正可运行的、容易移植的C代码。-Fifoed avalon uart IP core and C code for the IP core.
LCD1602_Driver
- 自己课设上写的基于Verilog的LCD1602驱动器，能自定义字符，16x2显示位均已引出，可以用于纯硬件的电子钟等显示-To write their own lessons based on the LCD1602-based Verilog driver can customize the character, 16x2 display spaces have led to, can be used for pure hardware such as an electronic clock
altera_up_avalon_sd_card_interface_91
- 修改后的Altera大学计划IP Core，可用于QII9.1及9.1SP1-Revised Altera University Program IP Core, can be used for QII9.1 and 9.1SP1
four_bit_full_adder_with_time_analysis
- four bit adder with time analysis and testbench