资源列表
add
- is a project that achieves a Full Add with VHDL on the platform XILINX
register
- this a project that makes a shift register using VHDL and the Xilinx platform. -this is a project that makes a shift register using VHDL and the Xilinx platform.
Eng
- HDL Design, verification using HDL languidges
HEX_DISPLAY
- Simple vhdl descr iption to show numbers on 7-segment s on Altera DE2 board.
CORDIC_GeneralInfo
- CORDIC implementation
clockreverse
- 数字钟 能实现倒计时 小时和分钟的调整 复位和暂停倒计时-clock
tb_tx_modem
- test bench for tx modem to make simulation for ofdm based system
DHT22_v1.1
- 我以前曾发过V1.0版的，这是此版的修正版v1.1,修正了以前版本中的一个错误，即只能读一个数据后就再也读不出温度数据的错误。 这个是用Quartus II软件写的Verilog HDL语言写的与温湿度传感器DHT2x通信的代码. 里面有详细的注解. 主要用于DHT2x单线总线通信转换为8位并行总线通信,应用于具有外部8位总线访问功能的单片机直接读取温湿度数据. 此程序在EPM7128SLC-10中成功测试. -I' ve once spoke V1.0 version, whic
acum_hdl
- phase accumolator in vhdl & test bench for it for dds-phase accumolator in vhdl & test bench for it for dds
clock1
- 多功能数字钟实现闹铃，整点报时，校时，仿广播电台报时功能-multifuntional digital clock written in verilog
uart
- the uart model is used to design the synthies and beherival model in verilog fpga
statemechine
- We are using parameters is the test bench and passing them to the state machine using parameter passing We are using tasks to control the flow of the testbench We are using hierarchical naming to access the state variable in the state machine f