资源列表
round_three_stage
- 3 stage round arbiter using verilog
bram_test
- Hex file to Binary file conversion using VHDL
system_c_code
- Counter , adder , reset code using system c
eth_ocm_80_3
- MAC ethernet ip opencore
signaltapdebugging
- FPGA 逻辑分析仪signaltapII详细用法介绍与调试分析-FPGA signaltapII design and debugging
32bitBoothmultiplier
- 32位布思乘法器VHDL实现，2个32位数相乘-32-bit Booth multiplier VHDL implementation, two 32-digit multiplication
altera_up_avalon_irda
- Altera大学计划的红外通讯IP，avalon接口-Altera University Program of the infrared communication IP, avalon interface
UART
- the uart transmitter and receiver are used to design the data transmission for 8bit sipo and piso in verilog
mux
- the multiplexer program are designed 2:1 and 4:1 in verilog model
encoder
- the encoder are designed to two for switchcase and if else function in verilog
Decoder
- the decoder program are used to decode the data for 4:1 decoder using xilinix
fir
- 数字电路设计中的，fir滤波器设计，我做的是8位宽的，利用vhdl实现，附带了完整的代码，报告，我没有对我的信息进行删除，是希望大家能够诚实的利用这个代码，提高自身本领。-Digital circuit design, fir filter design, I am doing is 8 bits wide, using vhdl implementation, with a complete code, the report, I did not delete my information i