资源列表
vhdl_hdb3
- a VHDL source code on HDB3 encoder realaized in FPGA/CPLD
VGAPWM
- FPGA PWM control and VGA display use VHDL language with simulation.
fsmmoore
- vhdl CODE FOR moore MODEL AND mux
RAM.ZIP
- VHDL CODE FOR RAM AND ROM
hhtrunc
- Used to truncate the input signal
fir
- vhdl code for fir filter
PROG
- USED TO CALCULATE DELAY
MTC700_VGA.RAR
- VGA Code for an spartan 3e in vhdl with an ucf file. You will find everything in de zip
ITU_656_Decoder
- Aletra DE2开发板 ITU_656_Decoder-ITU_656_Decoder
EP2C8Q208SDRAM
- NIOS系统设计的SDRAM控制程序-NIOS system design SDRAM control procedures. . .
LCDfcout
- FPGA实现LCD显示的频率计，芯片为cyclone-FPGA realization of the frequency meter LCD display chip for the cycloneII
clock
- FPGA用lcd显示屏实现的24小时的计时器-FPGA with the lcd screen to achieve a 24-hour timer