资源列表
Phone-Call-Meters-by-Quartus9.2
- 本次设计主要基于FPGA器件完成了一个IC电话计费器的设计，其能够显示用户IC的卡值余额，并能够根据用户当前的话务种类和通话时间进行扣费，并将用户的实时余额和通话时间通过4位LED七段显示器显示出来。整个设计过程采用自顶向下的分块设计方法，即将整个电话计费系统分为电话计费、计时模块和显示模块两大模块，其各模块的实现是基于QuartusⅡ9.2平台使用DE0硬件描述语言编程实现的。-This design is mainly based FPGA devices completed a telep
sdram_verilog
- 基于verilog语言的SDRAM控制器-SDRAM controller based on verilog language
Using-fpga-implementation-SDI
- 用fpga实现SDI（ xapp1014-xilinx-sdi）赛灵思原厂资料-Using fpga implementation SDI (xapp1014-xilinx-sdi) Xilinx original data
fpga_song
- FPGA Verilog 纯硬件程序实现播放音乐！-Pure hardware program FPGA Verilog play music!
biaojue4
- 此代码实现4人表决功能，4人中有三人同意即为通过。-Four voting
vga control
- This tutorial familiarizes you with the Nios® II Software Build Tools (SBT) for Eclipse and the MicroC/OS-II development flow. The Nios II SBT for Eclipse offers designers a rich development platform for Nios II applications. The Nios II SBT for Ecli
LED-ZOU-MA-DENG
- 这是基于ALTERA MAX系列低端FPGA开发板的LED走马灯源文件。压缩包包含了可以运行的整个工程。环境为QUARTUS II。-This is based ALTERA MAX series low-end FPGA development board LED lantern source files. Compressed packet contains the entire project can run. Environment QUARTUS II.
XUELIEXINHAOFASHENGQI
- 基于ALTERA MAX系列FPGA的开发板的序列信号发生器源码。应该可以通用。设计环境为QUARTUS II。压缩包包含整个工程。-ALTERA MAX Series FPGA-based development board serial signal generator source. Should be universal. Design environment QUARTUS II. Archive contains the entire project.
ZIDONGSHOUHUOJI
- QUARTUS平台下，VHDL编写的自动售货机源代码。基于ALTERA MAX系列FPGA开发板。绝对原创。-QUARTUS platform, VHDL source code written in vending machines. Based ALTERA MAX Series FPGA development board. Absolutely original.
Verilog
- 七段数码管译码器.(Verilog)[FPGA]第一个Verilog程序,七段共阴数码管摸索了好几天,终于能完成敲入代码、综合、仿真、绑定引脚至下载的全套工作了 -. 七段数码管的lookup table module SEG7_LUT ( input [3:0] iDIG, output reg [6:0] oSEG ) always@(iDIG) begin case(iDIG) 4 h1: oSEG = 7 b1111
lab2
- 在FPGA平台下，使用逻辑分析仪观察正弦波发生器的工程文件-In the FPGA platform, using a logic analyzer observed sine wave generator project file
8255soucure
- vhdl实现8255源码 里面包含源代码 测试文件，demo例子-VHDl 8255