资源列表
clock
- digital clock, altera
vendingmachinesource
- vendigmachine vhdl 5files component
VHDL-vanding
- dotmatrix and beep sound use the code
basic-vanding-code
- basic vandig code vhdl
VHDL
- 用Verilog语言编写的基于Alter公司FPGA学习版的小程序-Verilog language Alter' s FPGA-based applet Learning Edition
8
- VHDL实验的程序，数字时钟，进行分秒计时，用数码管显示-VHDL experimental procedures, digital clock, for every minute timer with digital display
7
- VHDL实验程序，关于数码管的动态显示，非常有用-VHDL experimental procedures on digital tube dynamic display, very useful
BISHE
- VHDL程序，关于暖气片的自动控制，非常有用-VHDL program, with regard to the automatic control of radiators, very useful
DUO
- VHDL程序，关于电子琴的自动播放，非常有用-VHDL program automatically play on the keyboard is very useful
lagrange
- 对原信号进行拉格朗日插值运算，实现信号重采样-The original signal Lagrange interpolation operation, to achieve signal resampling
AD9288
- AD9288的器件图，参照资料自制。有需要的下载。-AD9288 device diagram, reference information homemade. There is a need to download.
Systemverilog
- 这个为systemverilog 的一个牛人的总结，是初学者必备的，很适合初学者运用的。-This is systemverilog a summary of cattle is essential for beginners, it is suitable for beginners to use.