资源列表
tron
- Tron game, a video game developed by VHDL.
DDRSDRAM_MT46V32M16TG
- ddr控制器 对DDR实现读写控制-ddr control
source
- 《Verilog HDL程序设计教程》程序例子 带说明。对于要精通学习Verilog HDL者，有重要的帮助作用，里面全是源代码，供大家学习参考。-" Verilog HDL Programming Guide" program example with instructions. For those who want to master learning Verilog HDL, there is a great help, which all the source code
veriloghdl
- verilog hdl硬件描述语言，其中讲述了十个例子，帮助大家学习verilog hdl硬件描述语言。-verilog hdl hardware descr iption language, which describes 10 examples to help you learn verilog hdl hardware descr iption language.
multi71
- 本例中应用vhdl实现与71的相乘，使用的是移位相乘的方法-Vhdl application in this case multiplied by 71 to achieve and use the shift method of multiplying
fufenjieqi
- 基于FPGA的复分接器，包括了M序列码的产生，2路数据复接，数据分接（包括巴克码的判断）。-FPGA-based compound splitters, including M sequence code generation, 2 channel data multiplexing, data tap (including the Barker code to judge).
AdditionCounter
- 一个带有异步复位和同步时钟使能的十进制加法计数器-Asynchronous reset and synchronization with a clock enable decimal addition counter
FullAdder
- 要求在Quartus II软件，利用VHDL完成层次式电路设计，电路中的元件可以用VHDL设计也可以用库元件连线构成再封装。借助EDA工具中的综合器，适配器，时序仿真器和编程器等工具进行相应处理。输入方法不限制。适配采用Cyclone系列的EP1C6Q240C8。要求综合出RTL电路，并进行仿真输入波形设计并分析电路输出波形。要求采用层次式结构设计。-Quartus II software requires the use of VHDL complete hierarchical circui
Quartus8.1_licence
- A way to evalulate Quartus 8.1
Quartus7.1_licence
- A way to evalulate Quartus 7.1
Quartus7.0_licence
- A way to evalulate Quartus 7.0
Quartus5.1_licence
- A way to evalulate Quartus 5.1