资源列表
digital-clock_VHDL
- 使用VHDL实现数字时钟，已在FPGA上验证-use VHDL to build a digital clock, has been validated on FPGA
CPU
- 哈尔滨工业大学，计算机专业，计算机设计与实践课程，CPU设计-Harbin Institute of Technology, computer professional, computer design and practical courses, CPU design
SEG
- 采用DE2 实现数码管递增 VERILOG-Using DE2 achieve the digital pipe incremental VERILOG
VHDLmimasuo
- 重置密码功能、密码开锁功能、输入清除功能、警报功能、钥匙切换功能-Reset the password function, password lock function, enter the clear function, alarm function, key switching function
VHDLled
- 用VHDL设计出一条“蛇”，在一排（四个）七段数码管上以八字形绕圈子，并能通过按键改变其运动方向-VHDL design a " snake" figure eight in a row (four) seven-segment digital tube to beat about the bush, and through the buttons to change its direction of motion
VHDLqiangdaqi
- 抢答器线路测试功能,第一抢答信号的鉴别和锁存功能,犯规警示功能,计时，计分功能-Responder line test function, the First Responder signal the identification and latch function, foul warning function, timing, scoring function
VHDLrsjiemaqi
- 设计中国移动多媒体广播中的RS解码器,该RS码采用码长为240字节的RS(240, K)截短码-RS decoder design in China Mobile Multimedia Broadcasting
VHDLtrafficlight
- 设计一个交通灯，在正常情况下指挥一个十字路口的交通，有红黄绿三种状态，每次绿（红） 灯为三十秒；拥有紧急情况按键，此时相应的道路将一直为绿灯，另一条路则为红灯。 -Design of a traffic light, to commanding a crossroads of traffic under normal circumstances, red yellow and green three states, each green (red) lights for thirty sec
ccd
- 自己写的一个tcd1209d的时序驱动代码，是用verilog语言编写的，可以借鉴-Of write a tcd1209d of timing-driven code, Verilog language, can learn from
ccd
- 一种ccd驱动程序，是verilog编写的。值得大家去学习。-A ccd driver is written in verilog. Worth to learn.
SF-CY3-FPGA
- SF-CY3 FPGA套件开发指南Ver3.00,要学习的同学值得看一看-SF-CY3 FPGA Suite Developer' s Guide Ver3.00, students to learn is worth a look
4wire-driver-of-FPGA
- ALTERA公司飓风二ep2c5与触摸屏的接口代码。-ALTERA Company hurricane ep2c5 with touch screen interface code.