资源列表
IIC-VHDL
- iic 总线在设计时要看你所使用的器件的传输或接收时序 只要会一个，其他的都一样 以下是我在一本书上看到的，感觉很不错，你看看就会用了 -as long as the will a the iic bus depends on the devices you use in the design of the transmission or reception of timing, other-like following, I saw in a book, I feel very g
8051
- 这个是8051单片机原代码，文件层次比较分明，可读性强，对于初学单片机的同学来说是个不错的参考代码。-This is the 8051 original code, file hierarchy is clear, readable, a good reference code for the microcontroller beginner students.
pipline
- 用verilog实现的流水线cpu,实现高效率的CPU基本运算-Pipeline cpu with verilog
IR
- 是对9016遥控器解码的一个Verilog程序。-A verilog file about the decoding of 9016 remote-control unit.
IR
- 对应遥控器（9016）的解码程序，用verilog硬件描述语言编写。-Averilog file about the decoding of the remote-control unit of 9016.
1024_FFT_IP
- 实现了1024点FFT的IP核,用起来很方便，直接调用即可-To achieve a 1024-point FFT IP core is easy to use, and can be called directly
jiaotongdeng
- 简易的交通灯程序，适用于刚接触VHDL的人学习，易懂好学。-Simple traffic light program, for people new to VHDL to learn, easy to understand studious.
pinlvji01
- 简单的频率计，对于初学者来说，在计数方面是一个很好地帮助。-Simple frequency meter, for beginners, in the count is a good help.
snake
- 贪吃蛇verilog实现了贪吃蛇游戏的全部功能，包括游戏声音，游戏中蛇的移动，显示界面-The Snake Snake game all functions, including the game sound verilog snake game mobile display interface
mult32
- 4-cycle 32bit-Multiplier that can be work in FPGA. Correct work is confirmed by SP605 FPGA from Xilinx.
faddsub
- FPU adder / subtractor it is confirmed to work at 32MHz by Spartan-6 SP605.
dds
- verilog编写的dds发生器，修改频率字可改频率-dds in verilog