资源列表
cpu
- VHDL编写的CPU源码，可嵌入SOPC系统开发-Prepared by the VHDL the CPU source, embeddable SOPC system development
timer_16bits
- 一个16位的定时器，用于系统时间调度,已经调试过，可以挂在avalonMM总线上。-an 16 bits timer,can userd for system s time dispatch.
SIMULATION-AND-SYNTHESIS-OF-TRIPLE-DES-BLOCK-CIPH
- This project presents FPGA implementations of the DES and Triple-DES with improved security against power analysis attacks. The proposed designs use Boolean masking, a previously introduced technique to protect smart card implementations from these
THDB_D5M_CD
- Terasic TRDB-D5M CD V1.2.0
mutil_cpu
- 主要设计了基于Nios_的双核处理器的设计与实现，内含QUARTUS工程文件，实现了两个CPU通过互斥核通讯的实验。EP2C5平台-Primarily designed dual-core processors based Nios_ the design and implementation of embedded QUARTUS engineering documents, to achieve a of two CPU mutex nuclear communications experi
dpsk_3rd
- 2DPSK调制与解调。学生实验使用，包括信号源模块、时钟源生成模块、信号调制模块，信号解调模块。 其中包含了边沿触发下的阻塞语句。 编译环境：Q2 11.0，编译语言：verilog，仿真软件：moelsim altera -2DPSK modulation and demodulation. The student experiments, including the source module clock source generation module, signal modu
bianma
- 用verilog编写的实现相位选择的DQPSK调制-Written in verilog DQPSK modulation phase selection
8.11-PSKVHDL
- FPGA芯片作为核心处理器，实现PSK调制与解调的功能-FPGA chip as the core processor, PSK modulation and demodulation functions
MASK-code---decode
- FPGA作为核心控制器，实现MPSK的调制与解调功能-FPGA as the core controller MPSK modulation and demodulation functions
SOPC-VideoFramework
- Altera SOPC VideoFramework with TRDB-DC2 and TFT-LCD
FPGA-multiplier-on-chip
- 典型实例11.5 FPGA片上硬件乘法器的使用 软件开发环境：ISE 7.1i 硬件开发环境：红色飓风II代－Xilinx版 本实例实现一个IIR滤波器，并在ISE里面进行仿真。 \rtl目录里面是源文件 \project目录里面是工程-Typical examples 11.5 FPGA chip hardware multiplier using the software development environment: ISE 7.1i hardware d
i2c_slave
- i2c slave interface， use xilinx fpag HDMI SDI-i2c slave interface