资源列表
conv_dencode
- 基于quartus软件的卷积译码算法，应用维特比译码算法完成-Convolutional decoding algorithm based on the quartus software.complete the application of viterbi decoding algorithm
DDS_shiyan
- 用quartus编程实现的直接数字频率合成器（DDS）-The quartus programming direct digital frequency synthesizer (DDS)
dianzizhong
- 用VHDL语言编写的数字电子钟的代码，在quartus上运行即可-Digital clock using VHDL language code can be run on in the quartus
chuanxingkou
- 串行口的发送程序，工程文件，仿真文件，验证可行-The serial port of the sending program, project files, simulation files
sdramtest
- vhdl语言编写读写三星SDRAM程序，包含读写控制程序，地址转化程序，测试模块程序-vhdl language, reading and writing the Samsung SDRAM program, contains the read and write control procedures address conversion program, the test module program
lcd1602
- lcd1602 介绍LCD1602显示控制的建模 包括分频、控制程序-lcd1602 describes LCD1602 display control modeling, including frequency, control program
graphicallcd_latest.tar
- It s a project in VHDL for interfacing a graphical LCD with an FPGA. The project is an open-source file.
digital-clock
- 基于fpga软件的数字秒表设计，非常有用的教学程序-Digital stopwatch design based on FPGA Software, very useful teaching program
JTAG_CPLD_project_1.pdf
- JTAG_CPLD_project source VHDL code ，适用于开发JTAG接口。此工程使用Altera EPM570 MAX II CPLD，包含硬件和软件描述。-JTAG_CPLD_project source VHDL code, suitable for the development of the JTAG interface. This project using the Altera EPM570 MAX II CPLD, includes hardware a
lineardecoder
- 7,4汉明码的译码程序，条理清晰，易读易懂-7,4 Hamming code decoding process, the clarity, easy to read and understand
rxtx
- 串行通信程序，程序稳定可靠，分为好多模块代码写的不错，值得参考，-Serial communication program, the program is reliable, divided into a lot of module code written well worth considering.
fenpin_odd
- verilog HDL写的6分频程序，通过48MHz晶振分出8MHz频率-6 divided by program Verilog HDL written separation of 8MHz frequency by 48MHz crystal oscillator