资源列表
qdq
- （1）用于竞赛强大的四人抢答器 （2）抢答开始后20秒倒计，倒计结束后无人抢答显示超时 （3）能显示抢答台号 （4）系统复位后进入抢答状态，能显示犯规警报-(1) is used to contest a powerful four Responder (2) to answer in 20 seconds after the start of countdown, countdown display time-out after no one to answer in (3) ca
Pentek.Sum06
- Pentek dociment about FPGA Radars
01269753
- Biometric IEEE paper1
DA_TLC5620
- fpga实验板上的实现DA,AD转换，按动按键，数码管显示增加-The realization of the board on fpga DA, AD transform, press the button, digital pipe display increased
8051IP
- 基于FPGA的8051单片机的IP核应用与设计。-The IP core is based on FPGA for 8051 single chip.
FPGA-based-hand-gesture-recognition-system
- FPGA based hand gesture recognition system
lcd_controler.rar
- 用FPGA设计12832中文液晶控制器,采用状态机的方式，提高稳定性！,FPGA cyclone control 12832LCD
verilog_DA_TLC5615
- verilog 写的硬件示波器设计检测频率为1K~10KHz-verilog 1K~10KHz test
jishi999999
- 程序实现6位计数器，000000~999999，有一个使能信号en,将使能信号en由FPGA的引脚68接入，使用信号发生器产生方波，en信号为1的时候计数器计数，对于输入方波的幅值调为3.3V，可发现计数器计数一段时间会停止，然后接着计数。-Program six counters, 000000 999999, an enable signal en enable signal en by the FPGA pin 68 access, using the signal generator t
XSA50-VGA-GAME
- vhdl simple vga ps2 game project
30IIC
- 30 FPGA通过接口IIC通讯，30 FPGA通过接口IIC通讯-30 FPGA through the interface IIC Communications, 30 FPGA through the interface IIC communication
electric_timer_qutus
- 用verilog语言编写，主要是在FPGA中实现一个简易电子表的作用，利用时钟实现控制六个数码管的显示-With verilog language, mainly in the FPGA the role of a simple spreadsheet, use the clock to achieve control of six digital display