资源列表
I2C_HDL
- I2C bus HDL source and testbench
modelsim-installation
- modelsim的安装指导,以及简单的介绍modelsim的使用-Modelsim installation supervision, and the simply introduc the use of modelsim
music
- vhdl语言编写代码 梁祝音乐播放 fpga实现-vhdl code written fpga realize Butterfly music player
HOLA
- A simple practice with fpga xc3s200 xilinx, shows the word HOLA on the four displays. The source code is very simple
UART_FIFO
- Verilog编写的串口配合FIFO的代码，对大家学习串口和FIFO有一定帮助-Verilog prepared with FIFO serial code, we learn the serial port and FIFO have some help
pwm
- Verilog 语言开发的PWＭ IP软核 验证实现了PWM 输出-Verilog language development of PWM IP verified to achieve a soft-core PWM output
DDS
- DDS同 DSP（数字信号处理）一样，是一项关键的数字化技术。DDS是直接数字式频率合成器（Direct Digital Synthesizer）的英文缩写。与传统的频率合成器相比，DDS具有低成本、低功耗、高分辨率和快速转换时间等优点，广泛使用在电信与电子仪器领域，是实现设备全数字化的一个关键技术。-DDS with DSP (digital signal processing), is a key digital technology. DDS is a direct digital fre
0.01s-Timer-designed-in-VHDL
- 该设计方案是用VHDL语言实现0.01s计时器，该方案列出了详细的开发过程和所有源代码，并虽有仿真结果-The design solution is to use VHDL language 0.01s timer, the program lists the detailed development process, and all source code, and although the simulation results
Introduction-_FPGA_mid2
- fpga的中级教程，中级2_数字电路基础，请认真学习-fpga intermediate tutorial, intermediate 2_ digital circuits based on carefully study
i2c.tar
- 是个I2C软核，使用verilog和vhdl实现的，含有testbench。-this is soft core of I2C in verilog rtl and VHDL.
hdlc_7960
- 基于Verilog的7960实现。主要实现曼彻斯特的编解码。采用的倍频采样的方法。-Based on the 7960 Verilog implementation. Main achieved Manchester encoding and decoding. Frequency sampling method used.
beep
- 用于蜂鸣器音乐演奏测试程序，可以根据实际需要更改程序！-Music performance test procedures for the buzzer, you can change the program according to actual needs!