资源列表
AES!
- AES algorithm very good code tested in xilinx ise tool
数字边沿鉴相器
- 数字边沿鉴相器 verilog源程序 -figures for 2500 phase-2500 verilog source digital phase detector verilog source
sdram-control
- 基于FPGA的SDRAM读写控制程序，由VHDL语言编写-FPGA-based SDRAM read and write control program, by the VHDL language
traffic
- max_plus开发的 有max_plus就可以直接运行的交通灯制作 用vhdl语言编写的-max_plus development of max_plus can direct the operation of traffic lights produced by VHDL language
logic-(3)
- Bluetooth connection between a pc and a Spartan 6 PModBT module
0827
- 这是一个实现用VHDL实现拨号报警的程序-This a realization of using VHDL ALARM procedures! !
FIR-AD-code
- this is a AD FIR implementation
VHDL
- VHDL code for QAM modulation
RS(31-19-6)
- reed-solomon译码器。共有7个文件，分别为译码器的7个模块。
VHDL
- 滤波器 VHDL 应用VHDL基于FPGA设计FIR滤波器-Application of VHDL-based FPGA VHDL filter FIR filter design
uart_model_verilog
- uart通信协议的设计参考，对于初学者可以以此为参考进行设计，代码可在仿真软件中验证（modelsim、VCS等）。-Uart communication protocol design reference for beginners can be used as a reference design, the code can be verified in the simulation software (modelsim, VCS, etc.).
IPCore
- 在quartus中使用IP核的实际例子与流程