资源列表
pgvhdl4
- vhdl code spwm programme
ldpc-code
- ldpc codes are low dencity paRity checking matrix to check the parity on matrix based g and h algorithm based on algorithm matrix input will be added to this code
beamformer
- beamformer filter characteristics -beamformer filter characteristics
VHDLSDRAMcommand.vhd
- 基于fpga的实现sram控制器的vhdl源代码，非verilog-sram controller VHDL source code
BlackJack
- 本人利用FPGA实现的二十一点游戏程序，其中顶层电路用sch文件给出，每个模块使用VHDL语言编写-I use FPGA blackjack game programs, including the top-level circuit sch file gives each module using VHDL language
sales
- 自动售货机，与现实生活中的售货机功能类似，可以自动进行找零-Vending machines, vending machines and similar real life, there is a function to automatically calculate the price of goods
I2C-code
- I2C总线协议 Verilog源代码.试过，没有错误！可以直接使用-I2C bus protocol Verilog source code. Tried, no errors! Can be used directly
pxp_tlm
- 采用CAST公司的IP核，写出了PCIE中tlm层的代码-use the case company IP code to write the code of tlm layer
VHDL
- 多人抢答器 源代码 实用 课程设计 用用VHDL语言-The source code for more than Responder practical courses designed for use with the VHDL language
fpgafifo
- 基于fpga 实现 fifo 基于FPGA的非对称同步FIFO设计-Fpga-based FPGA-based realization of fifo asymmetrical design of synchronous FIFO
PISO-NEW
- THIS FOR STORING PURPOSE. THE INPUT IS IN PARALLEL AND OUTPUT IS IN SERIAL.-THIS IS FOR STORING PURPOSE. THE INPUT IS IN PARALLEL AND OUTPUT IS IN SERIAL.
codestream
- 设计一个模块，从一个窜行数据流里检测出码流“11100”，这个模块包括reset,clk,datain及输出端pmatch-design a module from a trip data flow channeling Lane detected bitstream "11100", this module includes reset, clk, datain and output pmatch