资源列表
usb1.1phy
- USB 1.1 PHY的代码，verilog语言 USB 1.1 PHY的代码，verilog语言-USB 1.1 PHY code, verilog language USB 1.1 PHY code, verilog language
VeriRISC_CPU_Verilog
- Verilog硬件描述语言实现VeriRISC CPU。模块包含：8位寄存器，5位计数器，32*8 RAM，8位ALU，MUX，顺序控制器，时钟生成器。包含TB。-This code is to model a VeriRISC CPU. It incorporates several modules: 8-bit register, 5-bit counter, 32 by 8 RAM, 8-bit ALU, scalable MUX, sequence controller, and clo
DDS_sin
- 用VHDL语言实现DDS直接数字频率合成器的设计，采用正弦RAM表，可实现频率可控的正弦数字信号，编译、仿真通过。-VHDL DDS Direct Digital Frequency Synthesizer Design using sinusoidal RAM table achieve controllable frequency sinusoidal digital signal, compile, through simulation.
NiosII
- 很好的nois学习资料。非常实用。 -Nois good learning materials. Very useful. Nois good learning materials. Very useful.
ModelSim---Xilinx
- 很好的Xilinx编译的说明文档 CSDN的博客-Good documentation compiled Xilinx CSDN' s blog
verilogvideocollection
- verilog的视频采集程序，verilog的视频采集程序
MD5
- 哈希算法FPGA实现代码，采用MD5算法，并给出了仿真波形。-MD5 hashing algorithm for FPGA implementation code
fsl_net
- 基于FSL总线的以太网控制器,用于Microblaze系统-Ethernet controller based on FSL bus
IIC_Verilog
- IIC_Verilog 代码，用Verilog 描述IIC协议的-the code is descr ipt the iic use Verilog
trafficlight
- 基于FPGA的交通的verilog语言设计，包括红黄绿三种灯，东西为一个方向，南北为一个方向，分别有倒计时-FPGA-based traffic verilog language design, including the red yellow and green three lights, something in one direction, a north-south direction, respectively, the countdown
debounce_exchange_VHDL
- 时钟分配和分路传输功能的VHDL语言程序，用于程控交换机功能时钟分配和分路传输功能-Clock distribution and transmission functions of shunt procedures VHDL language for program-controlled switchboard function clock distribution and transmission functions of shunt
booth_multiplier_VHDL
- VHDL implementation of booth multipiler