资源列表
program
- examples of vhdl program
noise-cancellation-.vhd
- noise cancellation in vhdl format
lms-filter.vhd
- LMS filter how to write in VHDL form in simple logic
vhdl-code.vhd
- vhdl code example model
divider3
- 三分频器，占空比为非50 ，仿真过，可用。-Three divider, non-duty-cycle 50 , over the simulation can be used.
noise.vhd
- noise in vhdl format
FPGA
- fpga 学习资料，内容丰富，需要的马上下载了-fpga
ser_deser_config.tar
- This is MAX9263/64 serialiser deserialiser configuration driver using i2c to uart driver. In this irq is configured using FPGA and it has to port for various interfaces properly
fit.vhd
- fit implementation in VHDL
Image-Reduction-IP
- LABVIEW Program for Image REduction IP for FPGA
ctfysj
- 3-8译码器,BCD码转换10进制,计数器-3-8 decoder, 10 BCD switch 229, counter, etc.
risc_cpu-OK
- 夏宇闻 verilog数字系统设计教程源码 第二版，实现了简单的RISC CPU。印刷版有误，已改正。- A simple RISC CPU Verilog HDL source code. Work well.