资源列表
beeptest
- XILINX BASYS2实验板的程序，蜂鸣器程序，播放歌曲为梁祝-XILINX BASYS2 experimental board procedures, the buzzer procedures, play a song for the Lovers
TrafficLightsControl
- quartus II 下 VHDL语言实现交通灯的控制-quartus II vhdl Traffic Lights Control
HighSpeedParallelMultiple
- quartus II 下VHDL实现快速乘法器-quartus II VHDL High Speed Parallel Multiple
rs232a
- rs232 模块的收发测试,实现re232 的并串之间的转换，-this modle is the test progrom of rs 232
dianzhen
- 这是一个基于FPGA开发实验箱的汉字点阵显示的Verilog HDL程序，经过实验调试验证过的 -This is an FPGA-based development of experimental box character dot-matrix display Verilog HDL procedures, through experimental testing verified
Altera-FPGA_CPLD-Design
- Altera FPGA/CPLD设计（基础篇），非常好的 FPGA入门教程-Altera FPGA/CPLD design (Basics), very good FPGA Tutorial
iicslave
- iic代码 这个是作为从机是接受数据是没有问题的 我已经验证过是可以用的额 -iic this communication code fpga have a slave ,the code test ok
61IC_S5560
- 采用xilinx的FPGA制作的测频模块，通过并口传给单片机-Produced using the xilinx FPGA frequency measurement module, microcontroller via the parallel port pass
mult
- verilog编写的8x16常变量乘法器，可用quartus仿真-verilog prepared 8x16 often variable multiplier, available quartus simulation
modelsim
- 这是一个适合初学者学习的好文档 -a pdf
pseudo8
- 8位伪随机序列发生器设计，可以进行时序仿真和功能仿真-The design of 8 bits Pseudo-Random Binary Sequence,you can do Timing simulation and function simulation
MtoNgencount
- Consider a counter that counts from m to n and then wraps around. Derive HDL code for the counter. Use generics, M and N, for m and n of the counter.(Note: there should be one control as UP/DOWN such that when UP/DOWN=1 then counts UP and for 0 it co