资源列表
q5
- what is the output of this small program? ans- this will loop indefinitely. value of i in main() will never exceeds 1.
modem1
- It is a implementation of FSK, ASK, modulation.
SPORT
- Sport vhdl interface for DSP
VHDL_huffman_decoder
- This is a Huffman decoder with dynamic Huffcode tables. A Testbench for a jpg file is include.
FSK
- FSK调制与解调VHDL程序及仿真FSK modulation and demodulation process, and VHDL simulation-FSK modulation and demodulation process, and VHDL simulation
HDB3
- HDB3编码器与译码 HDB3编码器与译码-HDB3 encoder and decoder
FPGA
- FPGA的作品，比较正规的veilog代码-FPGA-works, a more formal veilog code
logicSythesisBuildGate.pdf
- 逻辑综合的一些使用tips，做芯片前端的要-Some of the use of logic synthesis, tips, do-chip front-end to have a good look
sdram
- SDRAM驱动器，自己项目利用的，已经经过实际验证-sdram controller
DDSTHEORY
- 详细介绍了DDS原理，文档容易理解，是硬件开发者不错的选择-Details of the DDS principle, the document easy to understand, is a good choice for hardware developers ....
VHDLscounter
- 通过VHDL自行设计的一个秒表共有4个输出显示，分别为、十分之一秒、秒、十秒、分，所以共有4个计数器与之相对应（3个十进制计数器，一个6进制计数器用来对十秒进行计数），整个秒表还需有一个复位信号和一个精确的10HZ时钟信号。-Of a self-designed by VHDL stopwatch showed a total of four outputs, namely, one-tenth of seconds, seconds, ten seconds, minutes, so a to