资源列表
VHDL-Code-For-BCD-To-Excess3--Code-Converter-By-D
- VHDL Code For BCD To Excess3 Code Converter By Data Flow Modelling-VHDL Code For BCD To Excess3 Code Converter By Data Flow Modelling
fsk_final
- A simple FSK code using CORDIC sine wave generator.It is basically a switching oscillator kind of Frequency shift keying
VERILOG_FAQ
- Verilog FAQ ------------ This document contains 97 frequently asked questions and their answers related to Verilog. It s for novice to Verilog. But it also useful for intermediate Verilog programmer.
zhong
- 数字钟，实现整点报时以及校时功能，烟大数字逻辑课程实验。-Digital clock, realize the whole point timekeeping and school function, smoke large digital logic course experiment.
fengming
- VHDL实现蜂鸣器唱歌，已验证通过，音乐文件采用ROM存储。-VHDL implementation buzzer singing, has been verified through.
traffic_light
- 基于VHDL语言的关于交通路灯的设计，实现现实生活中路*通灯控制-Based on the traffic lights VHDL language design, implementation, real-life intersection traffic light control
SPI_IF
- 本人编写的简易SPI协议，将8位数据和8位地址共16bit信息转换为1bit串行数据输出-SPI protocol
rs232_tr
- 自学的串口通信模块，包含接收模块，发送模块，波特率模块，顶层模块-RS232 communication application,VHDL code
parallel8_serial
- V5 FPGA中8:1并串转换输出，可供初学者参考设计，涉及 OSERDES 原语的使用-the use of "OSERDES"
mcp2510_13.3
- this file function is to driver the chip of MCP2510
moonCar
- 实现小车的寻线（白线或者黑线）的代码，如何转向，判断是否偏离路线-Achieve trolley hunt (white line or black line) of the code, how to turn, determine whether the deviation from the route
Micro16-30sep03
- Micro16 - 一个简单的 16 位 VHDL CPU 核源代码-Micro16- A Simple 16 bit VHDL CPU source code