资源列表
TRAFFIC_LED
- 这个文件时quartus2下面实现了一个交通红绿灯的实现，有一些调试文件，放在quartus2下可以直接运行！相当的给力！-This file implements a quartus2 following the implementation of traffic lights, there are some debug file may be run directly on the quartus2! Equivalent to the force!
Protel99_lib_ALTERA
- 比较全的ALTERA芯片的原理图和封装库(Protel99)，对需要画Altera FPGA PCB版图的同志很有用。-Comparing all the ALTERA chip schematic and footprint library (Protel99), on the need to draw Altera FPGA PCB layout comrades useful.
FPU
- Verilog HDL code for implementation of double floating point architecture. Program takes care of diffent exceptions like overflow, underflow, NaN etc
myclock
- implement a 12-hour clock(This is a 12-hour digital clock, hout designates the hour, mout designates the minute, sout designates the second, and pout designates morning or afternoon. For example, if current time is 3:08:12 pm, then hout = 3, mout = 8
i2cdesign
- 这是我做的I2C的vhdl程序和仿真和下载文件，请指教！！！！1！1-This is what I do I2C procedures and the VHDL simulation and download files, please advise! ! ! ! 1! 1
ADDA_restored
- 一个AD采样，DDS产生的简易测试程序 HDL语言 Quartus测试程序
Phoenix3
- 数字密码锁的VHDL语言八位二进制，串行输入，有开锁和错误提示（LED） -code lock
DE2_LCM_Test
- DE2彩色LCM的Demo测试程序.包括DE2接口和驱动程序
VerilogHDL_Emample
- 其他说明： 文中实例基本都不依赖实际具体的硬件，可以在任何厂家任何系列的FPGA/CPLD下综合使用（如Altera等，只要资源充足），还可以利用Synoposy公司的工艺库影射到ASIC，完全可以当作软IPCore使用。 -Other notes: the text does not rely on practical and concrete examples of basic hardware, manufacturers of any series in any of the
VerilogHDLexample
- 可综合的VerilogHDL设计实例 ---简化的RISC CPU设计简介-VerilogHDL comprehensive design example can be simplified RISC CPU design--- Introduction---
eda-lab
- eda lab experiments-eda lab experiments....
wiznet5500_Verilog
- 使用Xilinx Spartan-6 XC6SLX9的FPGA驱动Wiznet5500网卡芯片的Verilog设计，可以发送和接收，已经测试，无误。-Using the Xilinx Spartan-6 XC6SLX9 FPGA driver The Wiznet5500 network card chip Verilog design can be sent and received, has been tested, and is correct.