资源列表
ADC_DAC_DESIGN
- ADC&DAC应用设计宝典，设计采样基本原理，相当经典的一本书-This book is very useful and classic for ADC & DAC design
usb_wr_Verilog
- fpga ubs通讯模块 verlog语言 使用EZ-USB FX2-USB interface. use EZ-USB FX2 carry out PC communication with FPGA by USB.
counter999
- 采用quartus软件的verilog编程语言编写的计数器模块-Counter module
basicVerilog
- 采用verilog编写的一些常用基本功能模块，带有PDF说明文档-Verilog prepared using some common basic function modules, with a PDF documentation
Binarydivider
- 采用verilog编写的二进制分频器,常用于频率变化场合-Binary frequency divider using verilog prepared, commonly used in the frequency occasions
32bitshiftregister
- 32位带锁存移位寄存器,采用verilog HDL语言编写，可用于串并转换-32-bit shift register with latches, using verilog HDL language can be used for string and convert
uart
- 基于verilog HDL编写的串口通讯接口uart程序-Prepared based on verilog HDL uart serial communication interface program
freq
- 应用VHDL语言设计低频数字频率计，选择测频法方案，主要是控制电路，由其产生闸门、清零和锁存等信号。-VHDL, design low frequency digital frequency meter, select the frequency method to program, mainly the control circuit, produced by the gate and the latch so clear signal.
MultifunctionDigitalClock
- quartus软件环境下采用verilog语言编写的多功能数字钟-quartus software environment using verilog language multifunction digital clock
zhjta
- 一个五层住户电梯的设计，这个电梯必须满足一般的功能，每一层都可以对其做上楼或下楼的选择-Five households in the design of a lift, the lift must meet the general function of each layer can be upstairs or downstairs of their choice to do
cpu
- 设计以及基本的CPU，至少包括四个基本单元，控制单元，内部寄存器，ALU和指令集-The purpose of this project is to design a simple CPU (Central Processing Unit). This CPU has basic instruction set, and we will utilize its instruction set to generate a very simple program to verify its perf
ditietickets
- 利用VHDL语言实现地铁售票系统的设计。售票系统根据途经站数自动计算票价-Using VHDL language metro ticket system. Ticketing system automatically calculated according to the number of fares via station