资源列表
verilog-procedures
- fpga的基于verilog的串行数据转并行数据的相关资料，相关内容uart协议，串并转换程序-verilog fpga-based serial data to parallel data, relevant information, relevant content uart protocol string and conversion program
dianhua-jifeiqi-verilog
- 电话计费器的verilog程序，希望对大家有用-Telephone billing verilog program
7duanyimaguan-Verilog-HDL
- 7段译码管的Verilog HDL程序，希望对大家有用-7 segment decoder tube Verilog HDL procedures
SIN-MODULATE-BASED-FPGA
- 对正弦波进行调制，下载到FPGA的硬件环境中，运行后用示波器检测，结果可行-On the sine wave modulation, downloaded to the FPGA hardware environment, running with an oscilloscope, and the results feasible
robot_control
- 机器人擂台赛。利用FPGA（EP2C5T144C8N）作为控制器，控制机器人实现避障、攻击其它机器人，以及清扫擂台。-Robot Challenge Cup. The use of FPGA (EP2C5T144C8N) as a controller to control the robot to achieve obstacle avoidance, attack other robots, as well as cleaning the ring.
verilog-codes
- xor code in verilog. can be used for fpga developement
fulladd4
- 全加器代码和测试激励文件，优化的全加器，占用FPGA资源少-Full adder code and test incentives
trafic
- traffic.v&test stimulas ,traffic control system
ddr_ram
- ddr_ram, ddr 工程调试文件，和测试向量激励-ddr_ram, ddr engineering code and test incentives document
ssl_decompose
- SSL安全协议解码源代码，和测试激励文件-SSL security protocol decoder source code, and test incentives document
pine_line_adder8
- 8 位全加器的设计，采用多pipeline设计方法-8 full adder multi-pipeline design
zigeti
- 基于FPGA的verilog语言写的按键控制步进1 的输出占空比从1 到99 的脉冲波，并用两位数码管显示出脉冲波占空比，按键key10加1 ,按键key11减1 。-FPGA-based verilog language button control stepper output duty cycle of 1 from 1 to 99 of the pulse wave, and use two digital tube display pulse duty cycle, key ke