资源列表
electronic-clock
- 基于FPGA的电子时钟的七段数码管显示+按键控制verilog程序-FPGA-based electronic clock seven-segment LED display+ button control verilog program
Barrel-shifter
- barriel shifter is used to design the unconfined shift. It has optional code to decide the logical function.also, you can decide the bit your shifter.
combination-logic
- 简单的逻辑运算VHDL程序，内含具体的程序要求。对同一种逻辑功能运算做dataflow 和 behavior 两种不同的形式的编程，适于初学者对比学习，了解VHDL运算环境-Simple logic operations VHDL program containing specific procedural requirements. Right to do the same kind of logic function computing dataflow and behavior of tw
24sCountdown
- 基于CPLD的24秒倒计时 计时的窗口显示分为数码管和发光二极管两部分，其中二极管部分表示数码管后一位，.0-.9或.00-.09，故本计时器精确度可以提高到0.01s-Based on CPLD 24 seconds countdown Timing window displays and LED digital tube is divided into two parts, where the diode portion represents a digital tube, .0-
SystemVerilog-Assertions-source-code
- SystemVerilog Assertion 应用指南一书的每章断言源代码，很好的SVA学习资料-SystemVerilog Assertion Application Guide for each chapter of a book asserts the source code, a very good learning materials SVA
lut
- 可参数化配置的CAM模块，仿照xilinx IP core设计而成，使用SRL16E基本单元实现，节省空间-Can be parameterized configurable CAM module, modeled xilinx IP core designed, implemented using the basic unit SRL16E, space-saving
I2C-master-Architecture.v1.1
- Architechture for I2C master to design the VHDL code
Cyclone4_115_TV
- 基于Altera cyclone4_115芯片下的完整VGA端口开发工程，包括VHDL源文件，和项目工程文件，对于FPGA下的VGA端口开发很有参考价值。-Based on Altera cyclone4_115 chip under full VGA port development projects, including the VHDL source files, and project files, the VGA port for FPGA development of great r
Cyclone4_115_IR
- FPGA下红外收发项目工程，基于cyclone4 芯片，包括项目verilog源码已经sof下载文件，对于基于fpga的红外模块开发很有参考价值。-Project under infrared transceiver FPGA based cyclone4 chips, including project sof verilog source code has been downloaded files for fpga-based infrared module development of
DCT_IP_Testbench
- 一个DCT变换的完整IP，基于Verilog编写，同时包括完成的testbench，方便模块的仿真和测试。-DCT transform a complete IP, based on Verilog prepared, including both complete testbench, convenient module simulation and testing.
Signal3
- ISE设计的三角波发生器VHDL实现及报告-ISE Design of the triangular wave generator VHDL implementation and reporting.
T
- T触发器 T触发器VHDL实现及报告 FPGA-T flip-flop VHDL implementation and reporting.