资源列表
ip_digifrec
- The Digital IF Receiver megafunction combines a quadrature NCO and a digital mixer to translate the input IF signal down to baseband
AD6635
- The AD6635 is a multimode, 8-channel, digital Receive Signal Processor (RSP) capable of processing up to four WCDMA channels
polyphase
- The current portion of the collaboration has involved the feasibilty and implementation of a Polyphase Filter bank using various FPGAs and hardware architectures
CPU
- CPU的构造，采用veril语言 对计算机专业同学有用-CPU
VerilogLangRefManual
- Simulation results show that energy savings in the range 30–60 and 10–60 are achieved in equalization and decoding, respectively. Furthermore, we present finite precision requirements of the linear turbo equalizer and an efficient rescaling metho
RECURSIVEALGORITHMFOREFFICIENTMAPDECODING
- Early termination enables powering down parts of the soft-input soft-output (SISO) equalizer and decoder thereby saving power.
MapAlgorithm
- However, turbo equalizers can be computationally complex and hence require significant power consumption. In this paper, we present an energy-efficient VLSI architecture for such linear turbo equalizers. Key architectural techniques include elimi
IterativeDecodingofBinary
- In this paper, energy efficient VLSI architectures for linear turbo equalization are studied. Linear turbo equalizers exhibit dramatic bit error rate (BER) improvement over conventional equalizers by enabling a form of joint equalization and deco
EnergyEfficientVLSIArchitectureforLinearTurboEqua
- Energy efficient for turbo encoder decoder
arm9_fpga2_verilog
- arm9 FPGA VERILOG 代码-arm9 FPGA VERILOG code
t1
- tourbo encode pdf file we can study derive these folders
Twister_DDR_SDRAM_Board_Manual
- Twister DDR EP1C6Q240 FPGA 开发板 原理图，PCB,BOM-Twister Board Documentation Schematics, PCB and BOM Rev. B