资源列表
s_p
- 用Verilog HDL语言进行并串转换，并通过Quartus Ⅱ 功能仿真验证-With the Verilog HDL language and string conversion functions through simulation Quartus Ⅱ
kbmjsq
- 用Verilog HDL语言实现可变模计数器的功能，并通过Quartus Ⅱ 功能仿真验证-Variable with the Verilog HDL language to counter the function module and function through simulation Quartus Ⅱ
zmstz
- 用Verilog HDL语言实现正码速调整的功能，并通过Quartus Ⅱ 功能仿真验证-Verilog HDL language used is code rate adjustment function, and functional simulation by Quartus Ⅱ
asyncRst
- 异步复位的同步化处理，对于asic设计尤为重要-Asynchronous reset the synchronization processing is particularly important for asic design
ep1c6_29_dds
- 此程序为一实现DDS的程序，很好的用VHDL语言编写。-this is a dds program by VHDL .Tt is a very accutate program.
fenpin
- 时钟分频器，初学者可以下载学习，效果比较好-Clock divider, beginners can download the study results were quite good
fskcodec
- fskcode 和fskdec，需要这方面的可以下载做练习-fskcode and fskdec, need this to do the exercises can be downloaded
cmicodec
- CMI编码和解码，对设计有很大的帮助，适用于学习和设计-CMI encoding and decoding, on the design of great help for study and design
FFT
- FFT的源程序， FFT的源程序-FFT of the source code, FFT of the source code, FFT of the source
askcodec
- ASK编码和解码源程序，可用于学习和设计中-ASK source encoding and decoding can be used in learning and design
dds_rom
- 此为Verilog编写DDS时，常用模块，为rom模块。-This is the Verilog write DDS, the common module, the module for the rom.
filter_200us
- 此为Verilog编写的延迟200US的程序，为Verilog常用模块。-This is written in Verilog delay 200US procedures used for the Verilog module.