资源列表
datacompresstion12
- jpeg velrilog code its a very good project for mainproject
EDAVHDL
- VHDL硬件描述语言 MAX+PLUSⅡ介绍 CPLD数字发展实验系统简介以及十个数字电路和数字系统实验的源代码和介绍-VHDL hardware descr iption language introduced the MAX+ PLUS Ⅱ Introduction CPLD digital development of experimental systems, as well as 10 digital circuits and digital systems, the source c
plj4
- 频率计，输入信号的频率最大不能超过9999Hz-Frequency meter, the input signal frequency maximum can not exceed 9999Hz
pptest
- vhdl代码的乒乓球游戏程序，使用de2平台验证-vhdl code of the table tennis games, platform verification using de2
DDS_Project
- 用VHDL书写的DDS程序 里面有详细的注解
PS2-VGA
- VHDL- introduce keywords from keyboard and displaying on a VGA display
trrfic_lamp
- FPGA设计的交通灯，四个状态自动跳转，用的数码管显示，不带紧急情况-FPGA design, traffic lights, four states automatically jump with digital display, without emergency
core_arm_latest.tar
- core_arm_latest.tar.gz源代码-core_arm_latest.tar.gz source code
PWM_music
- 在altera的FPGA平台上，使用verilog语言实现蜂鸣器的音乐，内含乐谱理论和verilog实现的FPGA奏乐代码与工程，已经测试通过，可以直接下载到FPGA运行，蜂鸣器播放音乐。-In the Altera FPGA platform, using Verilog language to achieve the buzzer music, FPGA music code and engineering including music theory and implementation
dds
- 用FPGA实现DDS,可变频,幅值由硬件完成
tlc5620dac
- 利用状态机实现对tlc5620dac控制，实验时按key1,可选择DAC的通道，数码管1显示，按key2，key3可 输入8位数/模转换值，由数码管3，4显示，按key4，选择输出电压模式，由数码管8显示，0表示1倍，1表示2倍，按key5,将当前数据发送到DAC模块启动一次DA转换，-State machine implementation control on tlc5620dac, press key1 experiment, you can choose the DAC channe
09~chapter-05-lbist
- Slides from "VLSI Test arch" book