资源列表
clock
- verilog HDL 编写的时钟分频器-prepared by the clock divider verilog HDL
verilog
- 八路彩灯控制系统，彩灯可以实现，从左到右顺次亮，全亮后逆次序渐灭。（2）从中间到两边对称地渐亮，全亮后仍由中间向两边逐次渐灭。（3）8路灯分两半，从左至右顺次渐亮，全亮后则全灭。-Eight lanterns control system, the lantern can be achieved, from left to right sequence bright, full brightness gradually eliminate the inverse order. (2) fade
uartfifo
- 该实验主要实现一个串口发送器功能， 该发送器的数据是从FIFO中读取的。也就是说，只要FIFO中有数据，串口发送器就会启动，将数据发送出去。 -The main experimental realization of a serial transmitter function, which sends the data is read the FIFO. In other words, as long as there is data in the FIFO, serial transmitt
LCD-1602
- VHDL语言实现的 简单LCD1602显示程序 很有参考价值-Simple VHDL language LCD1602 display program of great reference value
64pointFFTR2MDC
- 该工程实现了一个64点DIF FFT，verilog编写，采用R2MDC结构，通过Modelsim功能仿真，压缩包里有rtl代码，dc脚本，输出报告。-The project implements a 64-point DIF FFT, verilog compiled by R2MDC structure, through the Modelsim functional simulation, compression bag with rtl code, dc scr ipt, the out
PLD
- vhdl语言实现cpld功能，本程序包括全加器，触发器，交通灯程序，适用maxII软件调试。-include full_adder,plus,traffic
ad
- 这是用vhdl语言实现ad转换的源码，用quartus实现。(ad transform using vhdl)
HW1_alu_v1
- Arithmetic logic unit (ALU)是在電腦處理器之中其中一個組成單元,ALU 有 數學、邏輯、還有一些設計過的運算在電腦之中。(8-bit ALU Design is an unit of computer, it can process computation and logic.)
Security-System
- The security system implemented monitors the state of eight doors (open or closed) and shows the state in leds when the selector indicate it. Also the number corresponding to the desired door is shown in a 7seg display.
freq_counter_map
- 带有单片机接口的 频率计 经本人测试 功能正常 -Frequency counter with a single-chip interface through my test function was normal
I2S
- 用verilog实现的 I2S 源码，可以直接通过Quartus运行-I2S implementation by verilog source code can be run directly through the Quartus ~ ~
lab3_1
- VHDL利用四位拨盘输入数据，输入两个数，显示于数码管，另两个数码管显示其取反，四个数字再留个数码管上以一秒为周期左移-VHDL use four dial input data, input two numbers displayed on the digital control, the other two digital display its negation, then leave a four-digit digital tube left at one-second cycle