资源列表
I2Csimulatedfiles
- i square c - vhdl program for i square c
state
- verilog语言编写的高效状态机设计，值得好好学习一下-verilog language efficient state machine design, it is well to study the
state-machine
- pdf描述状态机的基本概念，外加三种状态的源代码-state machine
FPGA_Uart
- FPGA程序，verilog HDL语言编写，包含AD转换和串口发送程序，由于AD芯片种类繁多时序迥异，故主要参考串口发送程序。本程序使用quartus ii 13.0 编写。-FPGA procedures, verilog HDL language, includes an AD converter and serial transmission program, since a wide range of AD chip timing are different, so the main
esm
- 详细介绍了三种高效状态机设计，其中还有PDF格式的说明（英文版）。-Detailed information on the status of the three high-performance design, including descr iption of PDF format (in English).
verilog-course-design
- 两个关于Verilog语言学习的课程设计，有要求、思路和代码，一个是芯片接口设计，一个是智能烧烤机设计-Two on the Verilog language learning course design, requirements, ideas and code, a chip interface design, a smart barbecue machine design
zhuanghuang
- FPGA控制68013进行数据传递，采用被动传输方式-FPGA control 68013 for data transfer, the use of passive transmission
DDR_SDRAM.rar
- DDR RAM控制器的VHDL源码, 实现平台是Lattice FPGA,DDR RAM controller VHDL source code, the realization of Lattice FPGA platform is
paobiao
- 在FPGA上跑表功能的实现，具有从毫秒，微秒，到秒的计数过程，可以在开发板上进行仿真。-Stopwatch functions implemented in the FPGA, with the counting process milliseconds, microseconds to seconds, can be simulated in the development board.
FPGAdesign
- fpga设计大礼包，包括详细的流程介绍，引脚分配方案，设计思想等
sine-generator
- ROM型正弦信号发生器，从rom中读取正弦波的点，循环输出，经AD生成波形，环境为quartus-sine generator in quartus
74HammingCode
- 用VHDL语言编写的可以实现（7，4）汉明码编解码的程序。-Using VHDL language can be achieved (7,4) Hamming Code Codec procedures.