资源列表
Verilog HDL设计练习进阶
- 初学verilog HDL时 找的好资料 大家共享-Beginners should try to find a good share information
ddr_verilog_xilinx
- xilinx公司原版的DDR时序控制源码.-xilinx' s original source code of the DDR timing control.
ACTIVEHDL
- In this module we prepare our students to familiar with ACTIVE-HDL TOOLS, which is used for Compilation and Simulation purpose.
SIM
- VGA显示的工程文件，你必须下载上一个ISE文件，再下载下一个SRC文件才能正常运行-Project file, you must download the previous ISE files, and then download the next SRC file to run properly
RNG
- Random number Generator based in vhdl
frequency
- 能够检测方波正弦波以及锯齿波的频率，并且以及试过可以运行，采用的开发环境是ISE，编程语言是Verilog-Able to detect a square wave frequency of the sine wave and sawtooth wave, and as well tried can run the development environment is the ISE, the programming language is Verilog
EasyFPGA060_Routine_Comparator
- EasyFPGA060 比较器实验例程和文档-EasyFPGA060 comparator test routines and documentation
dds_sin
- 基于FPGA的DDS信号发生器，可以在FPGA上实现正弦波的产生，用到isp协议，sin函数rom发生器，希望这些能帮助大家！-FPGA-based DDS signal generator, sine wave generation on the FPGA, used isp agreement, the sin function rom generator, I hope These can help you!
sell-machine
- verilog sell machine 通过robei和vivado设计的建议xilinx测试程序，有助于学习vivado和fpga-verilog vivado xilinx
cnt100
- 一百进制计数器，采用层次化设计，底层文件为十进制计数器，顶层文件原理图设计-the procedure is based on vhdl,it can count 100,and use top-down
VGAcaisexinhaokongzhiqixiugaiban
- 这个是我们的课程设计，通过在网上寻找相关资料，设计出了行场扫描电路模块和颜色编码模块，然后设计整体顶层文件，最终实现VGA依次显示8种颜色的功能，其中，按键为MD，按一次，颜色变一次。-This is our curriculum design, through the Internet to find relevant information, to design a line of field scanning circuit module and color-coded blocks, a
I2C verillog
- I2C Verillog测试代码