资源列表
Chapter-5
- FPGA Prototyping by VHDL Examples Chapter 5
lab6_repeat
- Verilog adder of a four bit system. this adder adds four digit
N-BitComparator
- N-Bit Comparator Between X and Y
SouceCode_0f_DDR_SDRAM_Controller_by_VHDL
- VHDL语言编写的DDR RAM控制器的源码。-VHDL language source controller DDR RAM.
VHDL
- VHDL语言是一种用于电路设计的高级语言。它在80年代的后期出现。最初是由美国国防部开发出来供美军用来提高设计的可靠性和缩减开发周期的一种使用范围较小的设计语言 -VHDL language is a high-level language for circuit design. It appeared in the late 1980s. Was originally developed by the U.S. Department of Defense for the U.S. milita
ethernet_tri_mode.tar
- ethernet_tri_mode is used for ethernet conmunication.-ethernet_tri_mode is used for co ethernet nmunication.
RAM_DDS
- 使用硬件描述语言，在FPGA中实现直接数字频率合成-Use of hardware descr iption language, in the FPGA to implement direct digital frequency synthesis
DA
- Verilog HDL 写的１２位串口ＤＡ转换程序-Written in Verilog HDL conversion process 12-bit serial DA
Verilog_IIC
- 利用EP2C8Q208的FPGA芯片，利用Verilog硬件描述语言，实现对AT24C02的EEPROM进行读写操作。-The use of EP2C8Q208 FPGA chip, using the Verilog hardware descr iption language, the realization the AT24C02 of the EEPROM read and write operations.
RS232_NIOS_Verilog
- 5个文件，包含了RS232的nios实现和Verilog实现方式。其中,RS232的nios核实现只需要按照文件描述可以轻松实现^_^，个人比较推荐！RS232的Verilog实现需要编程，例程方便使用。RS232正在进一步学习中，有兴趣的可以探讨。-the realizition of rs232 interface by niosii uart ip core of Altera.it seems a most conveniet way.
traffic
- 交通灯控制程序，带左转功能，设置每个方向的控制时间不同，适合多种类型的-Traffic light control program with the functionality of a left turn, control time set for each direction, for a variety of types
CorrecaoProva2
- correction of test vhdl on ise