资源列表
Creating-Project-and-IP-Core-in-ISE
- 本文介绍了在ISE环境中如何新建工程，并且定义设置IP核进行开发-This article describes how new construction ISE environment, and define the settings IP core development
QPSK_SIM
- 实现QPSK的模拟-the simulation of qpsk
EDA
- 4位十进制计数器+7段数码管显示,有需要的同学可以参考一下！-4 decimal counter+7 of segment LED display
DDR_SDRAM_Controller
- DDR RAM控制器的VHDL源码，实现平台是Lattice FPGA，功能验证通过-DDR RAM controller VHDL source code, achieving the platform of Lattice FPGA, functional verification through
lcd1602
- verilog编写的LCD1602控制源代码，能够显示一串字符。-verilog source code written LCD1602 control, can display a string of characters.
Digital-frequency-meter
- 采用VHDL设计的数字频率计系统，测量频率范围在1HZ---10Khz，带有超量程报警和数码管分时扫描电路-VHDL design, digital frequency meter, measuring the frequency range of in 1HZ--- 10Khz, with over-range alarm and digital control of time-sharing scanning circuit
my_232
- 个人用verilog写的一个FPGA串口通信程序，程序测试成功，可以使用。-Individual by verilog written by one of the FPGA serial communication program that test, can use success.
POCPexperiment
- vhdl课程设计的POC程序，功能完整可直接执行，最终评为优秀-vhdl program designed POC program, full-featured to-run, and ultimately as good
DDR3的工作原理
- DDR3原理，详细的介绍了DDR3内部结构以及工作原理(DDR3 principle, detailed introduction of the internal structure of DDR3 and the principle of work)
ddr_verilog_xilinx
- xilinx的ddr sdram控制器文档-xilinx of ddr sdram controller documentation
final_6
- 6. 對於按鍵輸入密碼鎖，假設reset後，七節燈管顯示「0」，而且使用sw1、sw2二個，那麼只要sw2按下且放開後，七節燈管就顯示「2」，而只要sw1按下且放開時，七節燈管就更正顯示值「1」。-6. For the key to enter a password lock, assuming that reset after the seven lamp displays " 0" , and the use of sw1, sw2 2, then press and rel
bicycle
- 智能自行车 VHDL设计 顶层文件都已经画出-this is a smart bicycle system,you can use this system to done something