资源列表
DDS_DAC0832
- 基于verilogHDL语言DDS波形产生的程序，利用AD3092进行数据转换的-DDS-based waveform generation program verilogHDL language, using AD3092 data conversion
4fenpin
- 实现脉冲源A，B相4分频并实现4路计数功能。-Achieve pulse source A, B phase is divided by 4 and 4 to achieve counting.
dianzhao_dianzhen
- 使用altera的MAX2系列CPLD驱动16*32的双色点阵屏，包含“空车”，“重车”，“电召”三个字。driver.v文件用cpld驱动了东芝的TC62D748芯片，该芯片常用于扫描点阵的驱动上-The MAX2 series CPLD using altera-color dot matrix display driver 16* 32, with " empty" , " heavy vehicles" , " on-call" in t
06208897
- Reduced-Complexity LCCReed–Solomon Decoder Based on Unified Syndrome Computation
ARM_SOC
- ARM最小系统，vivado或ISE综合后下载至FPGA板子上可以做ARM用，包含连接在AHB总线上的RAM和ROM，ARM内核引出JTAG接口，可以连接调试器用keil-MDK进行调试！(ARM minimum system, vivado or ISE integrated download to the FPGA board can be used as ARM, including the RAM and ROM connected to the AHB bus, the ARM ker
基于DSP和FPGA的通用数字信号处理系统设计
- 利用DSP配合FPGA为硬件架构，以DSP为数据处理核心，通过FPGA对USB、ADC和DAC等外围设备进行控制，并可实现频谱分析、数字滤波器等数字信号处理算法。(With DSP and FPGA as the hardware architecture and DSP as the data processing core, the peripheral devices such as USB, ADC and DAC are controlled by FPGA, and the digi
PLJ-XIANSHI
- 自制频率计，可以设置频率分辨率以及测频范围，基于altera FPGA-Homemade frequency meter, you can set the frequency resolution and frequency measuring range, based on altera FPGA
sd_hd_sdi_good_using_micro8_CPU
- 美国Lattice公司的FPGA上实现的标清高清串行数字接口SDI的程序，使用到Micro8处理器，可以综合。-lattice FPGA to achieve the standard definition high-definition serial digital interface SDI program, the use of Micro8 processor on the FPGA.
heartbeat
- 用VHDL编译的源代码，模拟心脏跳动，解压后直接用Quartus打开project即可，不好意思刚才第一个那个模拟心脏跳动（heartbeat）的源程序发错了，请删除，-Compiled with VHDL source code to simulate the beating heart, after extracting the direct use of Quartus can open the project, I am sorry but the first one that simu
VHDLguoliangjiance
- 过零检测，输出部分有整数部分和偏移部分组成-Zero-crossing detection, the output part of the integer part and offset a part
para2serial
- 并串转换模块，用于serdes编码器后面的部分，转换后用于LVDS发送。-And string conversion module, part of the back of the encoder for serdes, after conversion to LVDS transmitter.
rom_read_modelsim
- Altera FPGA ，modulsim仿真rom读取，Quartus工程-Altera FPGA, modulsim simulation ROM read, Quartus engineering