资源列表
ROM
- 用于rom的存入地址，尽可能地增加稳定性-Rom the stored address for as much as possible to increase stability
AlteraFPGA
- AlteraFPGA_CPLD设计基础篇，值得一看-AlteraFPGA_CPLD Design Basics, worth a visit
chapter7
- VHDL 四位加法器 利用quartus II开发四位加法器，-VHDL comptur comparator_4
2-ask
- 2-ASK调制解调的FPGA实现。ASK-TWO为调制程序，two-ASK为解调程序。-2-ASK modulation and demodulation of the FPGA. ASK-TWO for the modulation process, two-ASK for the demodulation process.
ofdm
- ofdm调制解调的fpga实现。使用Verilog实现IEEE 802.16a系统的调制解调模块。-ofdm modulation and demodulation of fpga implementation. Verilog implementation using IEEE 802.16a system, modem module.
half_adde
- 半加器源代码，用VHDL语言编写有需要的可以-Half adder source code, using VHDL language need to look at
fulladde
- 全加器源代码，VHDL语言编写，有需要的参考参考-Full adder source code, VHDL language, the need to reference information
comp
- 经典比较器源代码，VHDL语言编写，可以-Classic source code comparator, VHDL language, you can see
SRAM
- SRAM源代码，VHDL语言编写，载入可编译，需要的-SRAM source code, VHDL language, incorporated in the compiler, we need to see
characters
- 一个是发送单个字符的，一个是发送任意长度字符串的-One is to send a single character, a string of arbitrary length is sent
61EDA_C2714
- xilinx ISE 4.1的入门，简单简单的。看看看看！-xilinx ISE 4.1, entry, simple simple. Look look!
crc_snd
- 串行数据的CRC校验，输出16位CRC校验码，通过仿真-CRC check serial data output 16-bit CRC check code, the simulation